텍트로닉스의 테스트 솔루션으로 PCIe 설계의 분석, 검증 및 사전 컴플라이언스 테스트를 가속화합니다.
송신기 및 수신기 테스트에 대해 장비 및 분석 소프트웨어를 제공하는 텍트로닉스 솔루션은 차세대 PCIe 사양(표준 1, 2, 3세대 및 현재 PCIe 4.0)에 대해 심층적인 분석, 컴플라이언스 테스트 및 디버깅을 수행할 수 있습니다.
- PCI Express®(PCIe) Gen1/2/3/4 송신기 솔루션 데이터 시트
- 업데이트된 사항! PCI Express®(PCIe) Gen3/4 수신기 CEM 솔루션 데이터 시트
- PCI Express®(PCIe) Gen3 수신기 기반 솔루션 데이터 시트
- PCI Express®(PCIe) Gen4 수신기 기반 솔루션 데이터 시트
- 새로운 소식! 수신기를 테스트하는 BSX 시리즈 BERTScope
- 송신기를 테스트하는 MSO/DPO70000 DX 오실로스코프(최대 33GHz 대역폭)
- 송신기를 테스트하는 DPO70000SX 오실로스코프(23GHz – 70GHz의 대역폭)
PCI Express에 대해 알아두어야 할 10가지 사항
유의해야 할 송신기 및 수신기 테스트 절차와 함께, PCIe Gen4의 새로운 기능 개요, 루프백 시작 및 프로토콜 핸드셰이킹을 비롯하여 포괄적인 디버그 프로세스 설정 시 필요한 핵심 고려 사항을 통해 계속해서 변화하는 표준의 중요한 측면을 이해할 수 있습니다.
Gen4 I/O 애플리케이션에서 수신기 테스트 문제 해결다운로드 »
보다 빠르게 PCI Express 컴플라이언스 이해지금 시청하기 »
|Overcoming Receiver Test Challenges in Gen4 I/O Applications|
This new application note provides vital information on performing compliance and diagnostic tests for Gen4 enterprise receivers with Bit Error Rate Testers.
|Logic Analyzer Fundamentals|
Learn the basics and benefits of logic analyzers - see how this tool can solve your debug challenges.
|Overcoming PCI-Express Physical Layer Challenges|
Using the powerful triggering and multiple data views of the Tektronix Logic Protocol Analyzer to overcome physical layer challenges.
|Understanding and Characterizing Timing Jitter Primer|
Timing jitter is the unwelcome companion of all electrical systems that use voltage transitions to represent timing information. This paper focuses primarily on jitter in electrical systems.
|Hunting PCIE Flow Control Bugs|
This white paper describes in detail the use of the Bird's Eye View (BEV), a completely new visualization, to investigate flow control.
|Triggering Fundamentals With Pinpoint® Triggering and Event Search & Mark for DPO7000|
This document discusses some fundamentals of triggering, and how Pinpoint triggering takes triggering in real-time oscilloscopes to a new level.
|PCI Express Probing Solutions with the Tektronix Protocol Analyzer|
This white paper discusses how to ensure proper board design and layout for digital debug and verification using the Tektronix PCIe Protocol Analyzer.
|PCI Express® Transmitter PLL Testing — A Comparison of Methods|
Overview of significant methods for performing PLL Testing
|The Basics of Serial Data Compliance and Validation Measurements|
This primer is designed to help you understand the common aspects of serial data transmission & to explain the analog and digital measurement requirements that apply to these emerging serial technologies
|Understanding the Transition to Gen4 Enterprise & Datacenter I/O Standards|
This whitepaper provides important information about adaptive equalization and link training, the impact of forward error correction (FEC) on compliance testing, debugging protocol handshaking and physical layer issues and new trends in channel performance evaluation along with other pertinent material when transitioning toGen4 standards.
|10 Things to Know about PCI Express|
Understand the important aspects of this continually changing standard with an overview of what’s new in PCIe Gen4, key considerations in setting up a comprehensive debug process, including loopback initiation and protocol handshaking, along with procedures of transmitter and receiver testing to keep in mind and more.
|Understanding Differences between PCI Express 4.0/5.0 and IEEE High Speed Electrical Specifications|
Our Tektronix domain experts, Dan Froelich and Pavel Zivny, contrast the methodologies of the PCI Express 4.0/5.0 and IEEE 26 GBd NRZ/PAM4 electrical specifications and engage in a lively discussion of the pros/cons of the approaches taken by each.
|Addressing PCIe Gen1-5 Test and Debug Challenges with Confidence|
Learn how to address the test and measurement challenges posed by PCIE Gen1-5 for both base silicon testing and CEM compliance testing. Gain insights and solutions for automation, validation, and debug for PCIE Gen1-5.
|Getting to PCI Express Compliance Faster|
This webinar will provide the information on test processes for PCIe devices to allow you to reach compliance faster.
|Overcoming Challenges in PCI Express Compliance Testing|
Learn the keys to debugging, verifying design and performing interoperability testing for PCI Express revisions 3.0 and 4.0.
|Maximizing Margins for 4th Gen High Speed Serial Standards|
As data rates increase, the effect of cables and fixtures become a larger part of the overall measurement result. Gain insight into the issues and how to solve them for each step of the signal path from the device under test to the oscilloscope.
|PCIe Gen 4.0 Rx & Link Equalization Test Procedure MOI|
This document cover the Method of Implementation (MOI) for PCIe Gen 4.0 Rx and Link Equalization Test Procedures.
|PCIe Gen 4.0 CEM Add-in Card PLL Bandwidth Test Procedure MOI|
This document cover the Method of Implementation (MOI) for PCIe Gen 4.0 CEM Add-in Card PLL Bandwidth Test Procedures.
|PCIe Gen 4.0 TX CEM Test Procedure MOI|
This document cover the Method of Implementation (MOI) for PCIe Gen 4.0 TX CEM Test Procedures.
|PCIe Gen 3.0 Link Equalization System and Add-in Card Test Procedure|
Tektronix PCI Express Gen3 Link EQ test MOI. This document cover Link EQ testing for both System DUT and Add-In Card.
|PCI Express 3.0 PLL Test MOI for Add-In Cards|
This document covers the Method of Implementation (MOI) for PCI Express 3.0 Phase-Lock-Loop (PLL) testing for Add-In Cards (AIC).
|PCI Express 3.0 Card Transmitter Test MOI|
This document covers the Method of Implementation (MOI) for PCI Express 3.0 CEM card transmitter testing, using DPO70000 Series Oscilloscopes.
|PCI Express 3.0 System Transmitter Test MOI|
This document covers the Method of Implementation (MOI) for PCI Express 3.0 CEM System transmitter testing, using DPO70000 Series Oscilloscopes.
|PCI Express 3.0 Receiver Test MOI for BASE Spec|
This document covers the Method of Implementation (MOI) for PCI Express 3.0 BASE receiver testing, using BERTScope instruments.
|PCIe Gen3 (8GT/s) Receiver Jitter Tolerance Test MOI|
This document covers the Method of Implementation (MOI) for PCIe Gen3 (8GT/s) Receiver Jitter Tolerance Test (Add-In Card and System) using Tektronix BSX Series BERTScope Bit Error Tester and ‘BERTScope PCIE3.0 Receiver Testing’ Application.
|Methods of Implementation (MOI) for Verification+ Debug and Characterization|
DPOJET Opt. PCE -- PCI Express Measurements & Setup Library