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PCI Express

텍트로닉스의 테스트 솔루션으로 PCIe 설계의 분석, 검증 및 사전 컴플라이언스 테스트를 가속화합니다.

송신기 및 수신기 테스트에 대해 장비 및 분석 소프트웨어를 제공하는 텍트로닉스 솔루션은 차세대 PCIe 사양(표준 1, 2, 3세대 및 현재 PCIe 4.0)에 대해 심층적인 분석, 컴플라이언스 테스트 및 디버깅을 수행할 수 있습니다.

Library

Title
Tektronix helps PMTC with compliance tests on high-speed buses
Solution SummaryChallengeTo enable one of Europe's leading multimedia test houses carry out compliance testing on high-speed serial buses including USB2, Serial ATA and PCIExpress.SolutionA suite of …
Understanding and Characterizing Timing Jitter Primer
Timing jitter is the unwelcome companion of all electrical systems that use voltage transitions to represent timing information. This paper focuses primarily on jitter in electrical systems..
The Basics of Serial Data Compliance and Validation Measurements
High-speed serial bus architectures are the new norm in today’s high-performance designs. While parallel bus standards are undergoing some changes, serial buses are established across multiple markets …
시리얼 데이터 적합성 및 검증의 기본
본 입문서는 시리얼 데이터 트랜스미션의 일반적인 사항을 이해하는데 도움을 주고자 만들어진 자료로 새로운 직렬 기술에 응용할 수 있는 아날로그 및 디지털 측정 요구 사항에 대해 설명하고 있습니다.
Triggering Fundamentals With Pinpoint® Triggering and Event Search & Mark for DPO7000
This document discusses the fundamentals of triggering and how Pinpoint triggering and Search and Mark takes triggering in real-time oscilloscopes to new levels of productivity.
PCI Express® Transmitter PLL Testing — A Comparison of Methods
There are several methods of measuring PLL loop response, based on the type of test instrumentation used. As expected, the various methods trade off test accuracy, test speed (throughput), ease of …
Logic Analyzer Fundamentals
Like so many electronic test and measurement tools, a logic analyzer is a solution to a particular class of problems. It is a versatile tool that can help you with digital hardware debug, design …
Understanding the Transition to Gen4 Enterprise & Datacenter I/O Standards
This whitepaper provides important information about adaptive equalization and link training, the impact of forward error correction (FEC) on compliance testing, debugging protocol handshaking and …
Overcoming PCI-Express Physical Layer Challenges
This paper will present how the Tektronix Logic Protocol Analyzer is used to overcome these challenges using powerful triggering and multiple data views.
Advanced Serdes Debug with a BERT
Learn simple strategies to pinpoint bit errors to the exact bit position and timing with powerful Error Location Analysis and a BERT.
Hunting PCIE Flow Control Bugs
This white paper describes in detail the use of the Bird's Eye View (BEV), a completely new visualization, to investigate flow control. Not only does the BEV provide a full-acquisition view of the …
Overcoming Receiver Test Challenges in Gen4 I/O Applications
This new application note provides vital information on performing compliance and diagnostic tests for Gen4 enterprise receivers with Bit Error Rate Testers.  
'최고의 파형 특성'과 '강력한 분석 능력' 고속 직렬 분석을 위한 최강의 파트너
디지털 직렬 분석기디지털 포스퍼 오실로스코프DSA/DPO70000B 시리즈20GHz - 50GS/s - 4채널 동시 DSA72004B-DPO72004B8GHz - 25GS/s - 4채널 동시 DSA70804B-DPO70804B16GHz - 50GS/s - 4채널 동시 DSA71604B-DPO71604B6GHz - 50 GS/s - 4채널 동시 …
Timing Error Debugging
New Designs, New HeadachesNew digital devices have become progressively more powerful by incorporating high-speed buses, subsystems, and logic families. They have also become more complex, more …
Time Domain Methods for Measuring Crosstalk for PCB Quality Verification Application Note
This application note discusses the elements of crosstalk and demonstrates how you can measure crosstalk on a single-layer PCB using the TDS8200 Series Sampling Oscilloscope or the CSA8200 Series …
PCI Express Probing Solutions with the Tektronix Protocol Analyzer
This white paper discusses how to ensure proper board design and layout for digital debug and verification using the Tektronix PCIe Protocol Analyzer.
타이밍 지터의 특성화 및 이해
타이밍 지터는 타이밍 정보를 나타내는데 전압 트랜지션을 이용하는 모든 전기/전자 시스템의 불청객입니다. 본 자료는 전기/전자 시스템의 지터 타이밍 문제를 주로 다루고 있습니다.
Title
Understanding Differences between PCI Express 4050 and IEEE High Speed Electrical Specifications
Our Tektronix domain experts, Dan Froelich and Pavel Zivny, contrast the methodologies of the PCI Express 4.0/5.0 and IEEE 26 GBd NRZ/PAM4 electrical specifications and engage in a lively discussion …
Addressing PCIe Gen1-5 Test and Debug Challenges with Confidence
Learn how to address the test and measurement challenges posed by PCIE Gen1-5 for both base silicon testing and CEM compliance testing. Gain insights and solutions for automation, validation, and …
Maximizing Margins for 4th Gen High Speed Serial Standards
As data rates increase, the effect of cables and fixtures become a larger part of the overall measurement result.  Cable and fixture effects can significantly reduce margins and thereby lead to …
Getting to PCI Express Compliance Faster
As design margins shrink, accurate and standard-specific measurement is key to debugging, verifying design and performing interoperability testing when designing PCIe devices. Having confidence in …
Overcoming Challenges in PCI Express Compliance Testing
Learn the keys to debugging, verifying design and performing interoperability testing for PCI Express revisions 3.0 and 4.0.
Title
Methods of Implementation (MOI) for Verification+ Debug and Characterization
This document provides the procedures for making PCI Express measurements with Tektronix DPO/DSA70000 Series Oscilloscopes with DPOJET (Jitter and Eye Analysis Tools) and probing solutions.DPOJET and …
PCI Express 3.0 PLL Test MOI for Add-In Cards
This document covers the Method of Implementation (MOI) for PCI Express 3.0 Phase-Lock-Loop (PLL) testing for Add-In Cards (AIC) using BERTScope CR125A, CR175A, or CR286A Clock Recovery instruments …
PCI Express 3.0 System Transmitter Test MOI
This document covers the Method of Implementation (MOI) for PCI Express 3.0 CEM System transmitter testing, using DPO70000 Series Oscilloscopes.
PCI Express 3.0 Receiver Test MOI for BASE Spec
This document covers the Method of Implementation (MOI) for PCI Express 3.0 BASE receiver testing, using BERTScope instruments.
PCIe Gen 4.0 Rx & Link Equalization Test Procedure MOI
This document cover the Method of Implementation (MOI) for PCIe Gen 4.0 Rx and Link Equalization Test Procedures.
PCI Express 3.0 Card Transmitter Test MOI
This document covers the Method of Implementation (MOI) for PCI Express 3.0 CEM card transmitter testing, using DPO70000 Series Oscilloscopes.
PCIe Gen 4.0 CEM Add-in Card PLL Bandwidth Test Procedure MOI
This document cover the Method of Implementation (MOI) for PCIe Gen 4.0 CEM Add-in Card PLL Bandwidth Test Procedures.
PCIe Gen 3.0 Link Equalization System and Add-in Card Test Procedure
Tektronix PCI Express Gen3 Link EQ test MOI. This document cover Link EQ testing for both System DUT and Add-In Card.
PCIe Gen3 (8GT/s) Receiver Jitter Tolerance Test MOI
This document covers the Method of Implementation (MOI) for PCIe Gen3 (8GT/s) Receiver Jitter Tolerance Test (Add-In Card and System) using Tektronix BSX Series BERTScope Bit Error Tester and …
PCI Express 3.0 De-embedding Method of Implementation Version 1.0
This document will provide a step-by-step procedure for extracting the Sparameters from the test channel of the PCI Express Gen 3 so it can be used for the purpose of removing the effects from the …
PCI Express 3.0 Receiver Test MOI for CEM Spec
This document covers the Method of Implementation (MOI) for PCI Express 3.0 CEM receiver testing, using BERTScope instruments. The document includes a step-by-step description of required hardware …
PCIe Gen 4.0 TX CEM Test Procedure MOI
This document cover the Method of Implementation (MOI) for PCIe Gen 4.0 TX CEM Test Procedures.