TLA600 Series Logic Analyzers

Tektronix Logic Analyzers
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Features & Benefits

  • 34/68/102/136 Channel Logic Analyzers With Up to 2 Mb Depth
  • MagniVu™ Acquisition Technology Provides 2 GHz (500 ps) Timing Resolution to Find Difficult Problems Quickly
  • Up to 200 MHz State Acquisition Analysis of Synchronous Digital Circuits
  • Simultaneous State and High-speed Timing Analysis Through the Same Probe Pinpoints Elusive Faults Without Double Probing and Reacquisition
  • 500 MHz Deep Timing Analysis with Up to 2 Mb Per Channel
  • Glitch and Setup/Hold Triggering and Display Finds and Displays Elusive Hardware Problems
  • Transitional Storage Extends the Signal Analysis Capture Time
  • Processor and Bus Support
  • Universal Source Code Support for Correlating High-level Language Source with Real-time Trace
  • Integrated View (iView™) Capability Works with Tektronix TDS Digital Storage Oscilloscopes for Analog/Digital Cross-domain Analysis


  • Digital Hardware Verification and Debug
  • Monitor and Measure Digital Hardware Performance

Breakthrough Solutions for Real-time Digital Systems Analysis

Today's digital design engineers face daily pressures to speed new products to the marketplace. The TLA600 Series logic analyzers answer the need with breakthrough solutions for the hardware design team, providing the ability to quickly monitor, capture and analyze real-time digital system operation in order to debug, verify and optimize their systems. TLA600 Series logic analyzers are affordable, entry-level logic analyzers, which are ideal for general-purpose state/timing analysis.

The TLA61x/62x logic analyzers feature front-panel controls, an integral display and support an external display simultaneously. The TLA60x logic analyzers utilize an external display.

Hardware developers appreciate the TLA600 Series logic analyzers' range of capabilities. Their broad feature set includes capturing and correlating elusive hardware faults by triggering on glitches and setup/hold violations; providing simultaneous state and high-speed timing analysis; and using state acquisition to find the cause of complex problems. Productivity and connectivity features, such as the open Microsoft Windows 2000 Professional PC platform, make the TLA600 Series logic analyzers easy to use and easy to network into the design environment.

All Tektronix TLA logic analyzers share the same TLA application software so that if you learn one, you can use them all. You can also share setups and data between them as well as display data on Windows PCs with the free TLAVu™ Offline Data Viewer.



Number of Channels (all channels are acquired including clocks) - TLA601/611/621: 34 channels (2 are clock channels).

TLA602/612/622: 68 channels (4 are clock channels).

TLA603/613/623: 102 channels (4 are clock and 2 are qualifier channels).

TLA604/614/624: 136 channels (4 are clock and 4 are qualifier channels).

Channel Grouping - No limit to number of groups or number of channels per group (all channels can be reused in multiple groups).

Time Stamp - 50-Bit at 500 ps resolution (6.5 day range).

Clocking/Acquisition Modes - Internal, internal 2X, external. 2 GHz MagniVu high-speed timing is available simultaneous with all modes.

Input Characteristics (with P6417, P6418 or P6434 probes)

Capacitive Loading - 1.4 pF typical data; 2 pF typical clock (P6418).

2 pF typical data and clock (P6417 & P6434).

Threshold Selection Range - From +5.0 V to -2.0 V in 50 mV increments.

Threshold Selection Channel Granularity - Separate selection for clock (1) and data (16) for each 17-Channel probe connector.

Threshold Accuracy (including probe) - ±100 mV.

Input Voltage Range - Operating: 6.5 Vp-p centered around the programmed threshold.

Non-destructive: ±15 V.

Minimum Input Signal Swing - 250 mV or 25% of signal swing, whichever is greater (P6417 & P6418).

300 mV or 25% of signal swing (P6434).

Input Signal Minimum Slew Rate - 200 mV/ns typical.

State Acquisition Characteristics (with P6417, P6418 or P6434 probes)

State Clock Rate - 100 MHz standard, 200 MHz optional.

State Data Rate (half/full channels) - 400/200 Mb/s, typical. Requires 200 MHz state option.

State Memory Depth with Timestamps - 64 Kb, 256 Kb, 1 Mb.

Setup Time Selection Range - From 8.5 ns before, to 7.0 ns after clock edge.

Setup-and-hold Window - 2.0 ns typical.

Minimum Clock Pulse Width - 2 ns.

Active Clock Edge Separation - 5 ns.

Demux Channel Selection - Channels can be demultiplexed to other channels through the user interface with 8-Channel granularity.

Timing Acquisition Characteristics (with P6417, P6418 or P6434 probes)

MagniVu™ Timing - 500 ps (2 GHz).

MagniVu Timing Memory Depth - 2 Kb per channel.

Deep Timing Resolution (half/full channels) - 2/4 ns to 50 ms.

Deep Timing Resolution with Glitch Storage Enabled - 10 ns to 50 ms.

Deep Timing Memory Depth (half/full channels with timestamps and with or without transitional storage) - 128/64 Kb, 512/256 Kb, 2/1 Mb.

Deep Timing Memory Depth with Glitch Storage Enabled - Half of default main memory depth.

Channel-to-channel Skew - ≤1 ns typical.

Minimum Recognizable Pulse/Glitch Width (single channel) - 2 ns.

Minimum Recognizable Multi-channel Trigger Event - Sample period +2 ns.

Trigger Characteristics

Independent Trigger States -  16.

Maximum Independent If/then Clauses per State -  16.

Maximum Number of Events per If/then Clause -  8.

Maximum Number of Actions per If/then Clause -  8.

Maximum Number of Trigger Events - 18 (2 counter/timers plus any 16 other resources).

Number of Word Recognizers -  16.

Number of Range Recognizers -  4.

Number of Transition Recognizers -  1.

Number of Counter/Timers -  2.

Trigger Event Types - Word, group, channel, transition, range, anything, counter value, timer value, signal, glitch, setup-and-hold violation.

Trigger Action Types - Trigger module, trigger all, store, don't store, start store, stop store, increment counter, reset counter, start timer, stop timer, reset timer, goto state, set/clear signal, do nothing.

Trigger Sequence Rate - DC to 250 MHz (4 ns).

Counter/Timer Range - 51 Bits each (>100 days at 4 ns).

Counter Rate - DC to 250 MHz (4 ns).

Timer Clock Rate - 250 MHz (4 ns).

Counter/Timer Latency - None (can be tested or reset immediately after starting).

Range Recognizers - Double bounded (can be as wide as any group, must be grouped according to specified order of significance).

Setup-and-hold Violation Recognizer Setup Time Range - From 8 ns before to 7 ns after clock edge in 0.5 ns increments.

Setup-and-hold Violation Recognizer Hold Time Range - From 7 ns before to 8 ns after clock edge in 0.5 ns increments.

Trigger Position - Any data sample.

MagniVu Trigger Position - MagniVu data is centered around the module trigger.

Storage Control (data qualification) - Global (conditional), by state (start/stop), by trigger action, or transitional.

Storage Window Granularity - Single sample or block-of-31 samples before and after.

Integrated View (iView) Capability

TLA mainframe configuration requirements - TLA6XX instruments.

TLA App S/W V 4.1 or greater.

256 MB DRAM Minimum, 512 MB recommended.

TDS configuration requirements - TDS3GM GPIB/RS232 Interface Module required for iView capability on any TDS3000 Series. TDS3GV GPIB/RS232/VGA Interface Module required for iView capability on any TDS3000B Series. If using iView with a TDS6604, order a TCA-BNC connector to be compatible with BNC cable run from a TLA7Axx module.

Number of TDS oscilloscopes that can be connected to a TLA system -  1.

External Oscilloscopes Supported - TDS3012, TDS3014, TDS3032, TDS3034, TDS3052, TDS3054.

TDS3012B, TDS3014B, TDS3032B, TDS3034B, TDS3052B, TDS3054B, TDS5052, TDS5054, TDS5104.


TDS7054, TDS7104, TDS7154, TDS7404.

TDS684C, TDS694C.

CSA7154, CSA7404.

TDS754C, TDS784C, TDS724D, TDS754D, TDS784D, TDS794D.

TLA Connections - USB, Trigger In, Trigger Out, Clock Out.

TDS Connections - GPIB, Trigger In, Trigger Out, Clock In (when available).

Setup - iView external oscilloscope wizard automates setup.

Data Correlation - After TDS oscilloscope acquisition is complete, data is automatically transferred to the TLA and time correlated with the TLA acquisition data.

Deskew - TDS and TLA data is automatically deskewed and time correlated when using the iView external oscilloscope cable.

iView External Oscilloscope Cable Length - 2 m.


TLA600 Series with TDS3000 Series oscilloscope.

TLA600 PC Characteristics

Operating System - Microsoft Windows 2000 Professional.

Processor - Intel Celeron.

Chipset - Intel 810.


Sound - Built-in PC speaker transducer; 16-Bit I/O and Mic In port.

Hard Disk Drive - 20 GB.

CD-ROM - Internal 16/8/32 CD-RW.

Floppy Disk Drive - Built-in 3.5 in. 1.44 MB drive.

TLA600 Integral Controls (TLA61x/62x only)

Front-Panel Display - Size: 10.4 in. diagonal.

Type: Active-matrix color TFT LCD with backlight.

Resolution: 800x600.

Colors: 16.8 M (true color).

Simultaneous Display Capability - The front-panel and external displays can be used simultaneously, each with independent resolutions.

Front-panel Knobs - Special function knobs for instrument control.

Front-panel QWERTY Keypad - Mini-QWERTY keypad.

TLA600 External Peripheral Interfaces

External Display Port Type - Female DB15 SVGA connector.

External Display Resolution - Up to 1280x1024 non-interlaced at 16 M colors.

LAN Port Type - 10/100Base-T, RJ-45.

External Keyboard Port Type - PS2 mini-DIN.

External Mouse Port Type - PS2 mini-DIN.

Parallel Interface Port Type - Female DB25.

Parallel Interface Modes - Centronics mode, EPP (Extended Parallel Port), ECP (Microsoft high-speed mode).

Serial Interface Port Type - Male DB9.

Audio Out Port Type - Stereo minijack.

Mic In Port Type - Minijack.

PC Card (CardBus) Slot Types - Two slots, two PC card type I/II or one PC card type III.

USB Port - One (1).


TLA60x Logic Analyzer with external display.


TLA61x/62x Logic Analyzer with internal display.

Symbolic Support

Number of Symbols/Ranges - Unlimited (limited only by amount of virtual memory available on TLA).

Object File Formats Supported -

  • IEEE695
  • OMF 51, OMF 86, OMF 166, OMF 286, OMF 386
  • COFF
  • Elf/Dwarf 1 and 2
  • Elf/Stabs
  • TSF (if your software development tools do not generate output in one of the above formats, TSF or the Tektronix symbol file, a generic ASCII file format is supported. The generic ASCII file format is documented in the TLA User Manual). If a format is not listed, please contact your local Tektronix representative.
External Instrumentation Interfaces

System Trigger Output - Asserted whenever a system trigger occurs (TTL-compatible output, back-terminated into 50 Ohm).

System Trigger Input - Forces a system trigger (triggers all modules) when asserted (TTL-compatible, edge-sensitive, falling-edge latched).

External Signal Output - Can be used to drive external circuitry from a module's trigger mechanism (TTL-compatible output, back-terminated into 50 Ohm).

External Signal Input - Can be used to provide an external signal to arm or trigger any or all modules (TTL-compatible, level-sensitive).


TLA60x/61x/62x - Voltage range/frequency: 90-250 VAC at 45-66 Hz.

100-132 VAC at 360-440 Hz.

Input current: 6 A maximum at 90 VAC (70 A surge).

Power consumption: 400 W maximum.

Physical Characteristics
























Net (w/o probes)



Shipping (typical)












Net (w/o probes)



Shipping (typical)




TLA60x Logic Analyzer with external display.


TLA61x/62x Logic Analyzer with internal display.


Temperature - Operating: +5°C to +50°C.

Nonoperating: -20°C to +60°C.

Humidity - 20% to 80%.

Operating: ≤30°C; 80% relative humidity (29°C maximum wet bulb temperature).

Nonoperating: 8% to 80% (29°C maximum wet bulb temperature).

Altitude - Operating: -1,000 ft. to 10,000 ft. (-305 meters to 3,050 meters).

Safety - UL3111-1, CSA1010.1, EN61010-1, IEC61010-1.


LACART Instrument Cart (adjustable probe skyhook not shown).


K4000 Instrument Cart.

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