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- Local Bus support for SDRAM and GPCM interface
- SDRAM (for PC133 and JEDEC-compliant SDRAM devices)
- GPCM memory cycles (General purpose chip select machine, for SRAM, EPROM and FEPROM memory types)
- DDR Bus Support includes: DDR reads or DDR writes cycles of DDR333 memory interface and Support for Both DDR333 reads and writes cycles simultaneously. Supports of debug signals on: MSRCID and ECC signals
- Supports many memory configurations: 14x11 / 14x10 / 13x11 / 13x10 / 13x9 / 12x10 / 12x9 / 12x8
- Supports CAS Latency adjustments
- Supports Big Endian and Little Endian byte ordering
Minimum System and Probe Requirements
Local Bus Support
- TLA7xx mainframe and one *TLA7N2 acquisition module, 68 channels, 200 MHz state or one *TLA7Ax2 acquisition module, 68 channels, 235 MHz state (up to 64 MB deep available).
- Qty 2: P6434High Density Compression Probes for TLA7N2 moduleli>
- Qty 2: P6860High Density Mictor Probes for TLA7Ax2 module
* Recommend using TLA7Ax4 modules
DDR Bus Support
- TLA application software v4.2
- TLA7xx mainframe
- One TLA7Ax4 acquisition module, 136 channels, 450 MHz state to support read or write cycles of DDR333 (up to 64 MB deep available).
- Two TLA7Ax4 acquisition modules, 136 channels, 450 MHz state to support read and write cycles of DDR333 (up to 64 MB deep available).
- Qty 4: P6860high-density compression probes to support read or write cycles of DDR333
- Qty 8: P6860high-density compression probes to support read and write cycles of DDR333
- Optional DDR hardware adapter/interposer (New Wave NEX-DDRHS)
- Instrument setup software including clocking and channel assignment
- Symbol table of all bus cycle names
- User manual
- Device description: PowerQUICC III Communication Processor Support
- Product number: TMS568