DTG5078 • DTG5274 • DTG5334

Data Timing Generator
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Features & Benefits

  • Versatile Platform Combines Features of Data Generator, Pulse Generator, and DC Source
  • Up to 3.35 Gb/s Data Rate
  • From 1 to 96 Data Channels (Master/Slave)
  • Class Leading Delay Resolution of 0.2 ps (DTG5274/DTG5334), 1 ps (DTG5078), up to 600 ns of Total Delay
  • Modular Architecture Helps to Protect Your Investment and Allows the Instrument to Expand With Your Growing Needs
  • Advanced Control Over Signal Parameters to Meet Most Current Testing Needs, Including Stressed Eye Generation
    • External Jitter Injection (DTGM31, DTGM32 Modules)
    • Level Control with 5 mV Resolution
  • Easy to Use and Learn, Shortens Time to Test
    • Easily Configure with Plug-in Modules
    • Intuitive Windows User Interface
    • Benchtop Form Factor
    • Integrated PC Supports Network Integration and Built-in CD-ROM, LAN, Floppy Drive, USB Ports
  • Up to 64 Mb Pattern Depth Per Channel for Complex Data Patterns

Applications

  • Semiconductor Device Functional Test and Characterization
    • Support for Semiconductor Technologies from TTL to LVDS
    • Initial Verification and Debugging, Comprehensive Characterization, Manufacturing, and Quality Control
  • Compliance and Interoperability Testing to Emerging Standards
    • PCI-Express Gen1:2.5 Gbps
    • Serial ATA Gen1/2:1.5 Gbps/3 Gbps
    • InfiniBand 2.5 Gbps
    • XAUI: 3.125 Gbps
    • HDMI: Version 1.3 / DVI
  • Magnetic and Optical Storage Design
    • Research, Development, and Test of Next-generation Devices (HDD, DC/DVD, Blu-ray)
  • Data Conversion Device Design
    • Characterization and Test of Next-generation D/A Convertors
  • Imaging Sensor Device Design
    • Characterization and Functional Testing of Next-generation Imaging Devices (CCD/CMOS)
  • Jitter Transfer and Jitter Tolerance Testing

New serial data standards, expanding networks, and ubiquitous computing continually redefine the cutting edge of technology. The design engineer is challenged to economize without sacrificing performance.

The DTG5000 Series combines the power of a data generator with the capabilities of a pulse generator in a versatile, benchtop form factor, shortening the duration of complex test procedures and simplifying the generation of low-jitter, high-accuracy clock signals, parallel or serial data across multiple channels. Its modular platform allows you to easily configure the performance of the instrument to your existing and emerging needs to minimize equipment costs. Three mainframes and five plug-in output modules combine to cover a range of applications from legacy devices to the latest technologies. In addition, eight low-current, independently-controlled DC outputs can substitute for external power supplies. Each mainframe incorporates a full compliment of auxiliary input and output channels to easily integrate with other instruments, such as oscilloscopes and logic analyzers, to create a flexible and powerful lab.

 

Characteristics

Mainframe Characteristics

Basic Features

Platform - Benchtop mainframe with cold-swappable plug-and-play plug-in output modules. Mainframes accept any combination of output modules.

Number of Slots for Output Modules -

DTG5078: 8 slots (A, B, C, D, E, F, G, H).

DTG5274: 4 slots (A, B, C, D).

NewDTG5334: 4 slots (A, B, C, D).

 

Master-Slave Capabilities -

DTG5078: Up to three DTG5078 mainframes can be connected in Master-Slave configuration.

DTG5274: Up to two DTG5274 mainframes can be connected in Master-Slave configuration.

DTG5334: Up to two DTG5334 mainframes can be connected in Master-Slave configuration.

 

Maximum Number of Output Channels

Number of Like Mainframes

DTG5078*1

DTG5274, DTG5334*1

DTGM21

DTGM30

DTGM31

DTGM32

DTGM21

DTGM30

DTGM31

DTGM32

1

32

16

3

8

8

4

2

64

32

6

16

16

8

3

96

48

9

*1 The DTG5078 has a limit to the number of modules that may be installed; the total must be less than 100. The coefficient for each module is shown below.DTGM30: 8, DTGM21: 10, DTGM31: 33, DTGM32: 32

Operating Modes -

Pulse Generator Mode (slots A to D only).

Data Generator Mode.

 

Output Patterns -

NRZ, RZ, R1, Pulse patterns (DTG5078/5274/5334: Slot A-D; DTG5078 Slot E-H, NRZ only).

 

Timing Parameters

Data Rate Range -

DTG5078:

NRZ: 50 Kb/s to 750 Mb/s.

RZ, R1, Pulse Mode: 50 Kb/s to 375 Mb/s.

DTG5274:

NRZ: 50 Kb/s to 2.7 Gb/s.

RZ, R1, Pulse Mode: 50 Kb/s to 1.35 Gb/s.

DTG5334:

NRZ: 50 Kb/s to 3.35 Gb/s (settable to 3.4 Gb/s)

RZ, R1, Pulse Mode: 50 Kb/s to 1.675 Gb/s (settable to 1.7 Gb/s)

 

Data Rate (Setting) Resolution -

Internal Clock : 8 digits.

External Clock : 4 digits.

External Phase Lock In : 4 digits.

 

Output Timing Controls

Delay Range -

PG Mode: 0 to 3 μs.

DG Mode:

Long Delay Off: 0 to 5 ns (NRZ, RZ, R1).

Long Delay On: NRZ:

Period ≥1.25 ns: 0 to 300 ns (Hardware sequence) or to 600 ns(Software sequence).

Period <1.25 ns: 0 to (240 ns × period) (Hardware sequence) or to(480 ns × period) (Software sequence).

Long Delay On: RZ/R1:

Period ≥2.5 ns: 0 to 300 ns (Hardware sequence) or to 600 ns(Software sequence).

Period <2.5  ns: 0 to (120 ns × period) (Hardware sequence) or to(240 ns × period) (Software sequence).

 

Delay Resolution -

DTG5078: 1 ps.

DTG5274/5334: 0.2 ps.

 

Phase Resolution - 0.1%

Differential Timing Offset Feature [between pair of two adjacent channels (Odd and Even)] -

Range: -1.0 to 1.0 ns.

Resolution:

DTG5078: 1 ps.

DTG5274/5334: 0.2 ps.

 

Semiautomatic Deskew Calibration -

Range: 500 ps.

Accuracy (after skew calibration):

100 ps, slots A to D.

200 ps, slots E to H (DTG5078 only).

 

Duty Cycle Adjustment Range - 0 to 100% (with 0 delay setting, RZ, R1, Pulse mode only).

Duty Cycle Adjustment Resolution - 0.1%.

Pulse Width Maximum Range - 290 ps to (period - 290 ps) (RZ, R1, Pulse mode only).

(Range also depends on delay settings.)

 

Pulse Width Resolution - 5 ps.

Jitter Performance (output channels)

Clock Pattern ("1010…" clock pattern)

Random Jitter -

DTG5078: <4 psRMS (at 750 Mb/s with DTGM21, 0.8 Vp-p, delay: 0.0 ns).

DTG5274: <3 psRMS (at 2.7 Gb/s with DTGM30, 0.8 Vp-p, delay: 0.0 ns).

DTG5334: <3 psRMS (at 3.35 Gb/s with DTGM30, 0.8 Vp-p, delay: 0.0 ns).

 

Data Pattern (PRBS pattern 215-1)

Total Jitter -

DTG5078: at 750 Mb/s

<18 psRMS, <85 psp-p (typical) with DTGM21, 0.8 Vp-p, delay: 0.0 ns).

DTG5274: at 2.7 Gb/s

<16 psRMS, <60 psp-p (typical) with DTGM30, 0.8 Vp-p, delay: 0.0 ns).

<14 psRMS, <60 psp-p (typical) with DTGM31, 0.8 Vp-p, delay: 0.0 ns).

DTG5334: at 3.35 Gb/s.

<15 psRMS, 50 psp-p (typical) with DTGM30, 0.8 V and DTGM31, 0.8 Vp-p, delay: 0.0 ns); <13 psRMS, 50 psp-p (typical) with DTGM31, 0.8 V and DTGM31, 0.8 Vp-p, delay: 0.0 ns).

<44 psp-p with DTGM30, Delay: 0.0 ns, Amplitude = 0.4 V p-p, Offset = 0.0 V, Data Format = NRZ, Jitter Mode = Off, an ambient temperature of 20 to 30 °C.

 

Signal Control Features

Cross-point Adjustment (duty cycle distortion) -

Range: 30% to 70%.

Resolution: 1%.

(Slots A to D, and DTGM30/M31/M32 used in NRZ mode.)

 

Jitter Generation -

Jitter All or Partial Pattern.

Jitter Profile: Sine, Gaussian Noise, Square, Triangle.

Jitter Freq./Res.: 0.015 Hz to 1.56 MHz / 1 mHz.

Jitter Amplitude: Up to 16.5 UIp-p (depending on data rate and jitter frequency).

(Internal Jitter Generation available on Channel A1 only.)

 

Pulse and Data Features

Pulse Generator (PG) Features (unique to PG mode) -

Continuous or Burst.

Burst Count: 1 to 65,536.

Pulse Rate: Off, 1/1, 1/2, 1/4, 1/8, 1/16.

 

Data Patterns

Pattern Length per Channel (Pattern Memory) -

Minimum:

DTG5078: 1 bit (software mode) or 240 bits (hardware mode).

DTG5274/5334: 1 bit (software mode) or 960 bits (hardware mode).

Maximum:

DTG5078: 8,000,000 bits.

DTG5274: 32,000,000 bits (in multiples of four).

DTG5334: 64,000,000 bits (in multiples of four).

 

Built-in Data Patterns - Binary Counter, Johnson Counter, Graycode Counter, Walking Ones, Walking Zeros, Checker Board, User-defined Patterns.

Pattern Import Capability -

Type/Tools:

Tektronix TLA Data Exchange Format File (*.txt).

Tektronix HFS Vector File (ASCII) (*.vca).

Tektronix HFS Vector File (binary) (*.vcb).

Tektronix AWG2000 Series (*.wfm).

Tektronix AWG400s/500s/610/710/710B (*.pat).

Tektronix DG2000 Series (*.dat).

Medium/Pass:

Import data through GPIB, LAN, CD-ROM, floppy drive, USB memory devices.

 

Pattern Copy and Paste Capability - Copy, paste, and rotation between data listing/waveform editor and spreadsheet software (e.g. Excel) through the clipboard.

PRBS/PRWS Data Patterns - (Note: Memory supports PRBS/PRWS patterns, and user can create errored PRBS)

25-1, 26-1, 27-1, 28-1, 29-1, 210-1, 211-1, 212-1, 213-1, 214-1, 215-1, 223-1.

 

Sequencer Features

Sequence Length -

1 to 8,000 steps for main sequence.

1 to 256 steps for subsequence.

 

Max. Number of Blocks - 8,000.

Max. Number of Subsequences - 50.

Repeat Counter - 1 to 65,536 or infinite.

Channel Addition - AND or XOR (slots A to D only).

Note: DTG5078 slots E, F, G, and H do not support the following: RZ, R1, pulse generation modes which includes controls for trail delay/duty cycle/pulse width, channel addition, and variable cross-points.

Auxiliary Channels

Clock Out

Connector - Complementary output (common offset and ground).

DTG5078/5274: SMA rear panel.

DTG5334: SMA front panel.

 

Frequency Range -

DTG5078: 50 kHz to 750 MHz.

DTG5274: 50 kHz to 2.7 GHz.

DTG5334: : 50 kHz to 3.35 GHz, settable up to 3.4 GHz.

 

Frequency Resolution -

8 digit setting resolution

Minimum: 1 mHz (e.g. with 50 kHz setting).

 

Internal Clock Accuracy - within ±1 ppm.

Jitter -

DTG5078: <2 psRMS at 750 Mb/s, at 0.8 Vp-p (typical).

DTG5274: <2 psRMS at 2.7 Gb/s, at 0.8 Vp-p (typical).

DTG5334: <2 psRMS at 3.35 Gb/s, at 0.8 Vp-p (typical).

 

Amplitude/Resolution -

0.03 Vp-p to 1.25 Vp-p / 10 mV (50 Ω).

0.06 Vp-p to 2.5 Vp-p / 10 mV (1 MΩ).

 

Output Voltage Window -

-2.0 to 2.47 V (50 Ω).

-2.0 to 7.00 V (1 MΩ).

 

Max. Output Current - ±80 mA.

Transition Times (20% - 80%) -

DTG5078:

<85 ps (Amplitude = 0.1 Vp-p, Offset = 0 V) (typical).

<100 ps (Amplitude = 1.0 Vp-p, Offset = 0 V) (typical).

DTG5274:

<70 ps (Amplitude = 0.1 Vp-p, Offset = 0 V) (typical).

<80 ps (Amplitude = 1.0 Vp-p, Offset = 0 V) (typical).

DTG5334:

<100 ps (Amplitude = 1.0 Vp-p, Offset = 0 V) (typical).

 

Overshoot - <10%, at High = 1.0 V, Low = 0 V into (50 Ω) (typical).

Other Output Channels

Auxiliary DC Outputs - -3.0 to 5.0 V / 10 mV, Max. current: ±30 mA, 8 independently controlled outputs, Connector: 2 × 8 pin header on front panel.

Sync Out - CML (current mode logic), VOH: 0 V , VOL: -0.4 V (50 Ω) (typical), SMA Connector, SE, Front panel, Rise/Fall Time (20 to 80%): 140 ps, Delay to Data Out: -4.5 ns (typical).

10 MHz Reference Out - 1.2 Vp-p (50 Ω, AC coupled) (typical), 2.4 Vp-p (1 MΩ, AC coupled) (typical), BNC Connector, Rear Panel.

Input Channels

External Clock In -

Input Ranges:

DTG5078: 1 MHz to 750 MHz. SMA connector, rear panel.

DTG5274: 1 MHz to 2.7 GHz. SMA connector, rear panel.

DTG5334: 1 MHz to 3.35 GHz. SMA connector, front panel.

0.4 Vp-p to 2 Vp-p (50 Ω, AC Coupled), 50% ±5% duty cycle.

 

10 MHz Reference In -

Input Ranges:

10 MHz ±0.1 MHz, 0.2 Vp-p to 3 Vp-p (50 Ω, AC coupled), BNC connector, rear panel.

 

Phase Lock In -

Input Ranges:

1 MHz to 200 MHz, 0.2 Vp-p to 3 Vp-p (50 Ω, AC coupled), BNC connector, rear panel.

 

Skew Cal In - Single-ended, ECL (into 50 Ω to -2 V), SMA connector, front panel.

Trigger In -

Input Ranges:

-5 V to 5 V (50 Ω), 0.1 V resolution, -10 V to 10 V (1 kΩ), Min. 0.5 Vp-p (50 Ω), 1.0 Vp-p (1 kΩ), Min. 20 ns pulse width, Positive or Negative edge trigger, Delay timing: see manuals, BNC connector, front panel.

 

Event In -

Input Ranges:

-5 V to 5 V (50 Ω), 0.1 V resolution, -10 V to 10 V (1 kΩ), 0.1 V resolution, Min. 0.5 Vp-p (50 Ω), 1.0 Vp-p (1 kΩ), Polarity: Normal or Invert, Delay timing: see manuals, BNC connector, front panel.

 

Instrument Control/Data Transfer Ports

GPIB - GPIB for remote control and data transfer. (conforms to IEEE 488.1, compatible with IEEE 488.2 and SCPI-1999.0).

LAN - LAN for PC interface, remote control, and data transfer (conforms to IEEE 802.3).

Computer System and Peripherals

Compact PCI-based PC, Celeron 566 MHz CPU, Microsoft Windows 2000 Professional, 128 MB SDRAM, 20 GB Hard Drive, 1.44 MB floppy drive on front panel, CD-ROM in rear panel, included USB compact keyboard and mouse.

PC I/O Ports

USB 1.1 compliant ports (3 total, 1 front, 2 rear), PS/2 mouse and keyboard connectors (rear panel), RJ-45 Ethernet connector (rear panel) supports 10Base-T and 100Base-Tx, VGA Out (rear panel), RS-232C.

Physical Characteristics

Mainframe Dimensions

mm

in.

Display Characteristics – LCD color display, 800 (H) × 600 (V) (SVGA).

Height

266

10.5

Width

445

17.5

Length

462

19.7

Output Module Dimensions

mm

in.

Height

33

1.3

Width

84

3.3

Length

133

5.2

Weight (approx.)

kg

lb.

DTG5078

17.5

38.6

DTG5274

17.0

37.5

DTG5334

17.0

37.5

DTGM21

0.26

0.57

DTGM30

0.27

0.60

DTGM31

0.27

0.60

DTGM32

0.27

0.60

Mechanical Cooling – Required Clearance

Top and Bottom - 2 cm.

Side - 15 cm.

Rear - 7.5 cm.

Power Supply

Power Source - 100 to 240 VAC, 47 to 63 Hz.

Power Consumption - 560 W.

Environmental

Characteristic

Operating

Nonoperating

Temperature

+10 °C to +40 °C

-20 °C to +60 °C

Humidity

20% to 80% relative humidity with a maximum wet bulb temperature of 29.4 °C, noncondensing

(no diskette in floppy drive): 5% to 90% relative humidity with a maximum wet bulb temperature of 40 °C, noncondensing

Altitude

3,000 m (10,000 ft.)

12,000 m (40,000 ft.)

Random Vibration

2.65 m/s2 RMS (0.27 GRMS), from 5 Hz to 500 Hz, 10 minutes

22.36 m/s2 RMS (2.28 GRMS) total from 5 Hz to 500 Hz, 10 minutes each axis 3-axes. 30 minutes total

Safety -

UL61010B-1.

CAN/CSA-22.2 No. 1010.1.

EN61010-1/A2 1995.

 

Electromagnetic Compatibility (EMC) -

Europe:

EN61326 Class A.

EN61000-3-2, EN61000-3-3.

Australia / New Zealand:

AS/NZS 2064.

 

Output Module Characteristics

Basic Features

DTGM21

DTGM30

DTGM31

DTGM32

Output Channels and Connections

4 single-ended (installed in DTG5078)

2 single-ended (DTG5274/5334)

4 SMA connectors

2 complementary channels

4 SMA connectors

1 complementary channel

2 SMA connectors

Maximum Data Rate (calculated by transition time)

1.1 Gb/s

3.35 Gb/s

350 Mb/s*2

Normal/ Complement (Invert)

Selectable

Source Impedance

50 Ω / 23 Ω (selectable)

50 Ω

Enable/Disable

Yes (software switch)

Output Channel Timing

Transition Times (20 - 80%) (50 Ω)

<340 ps (VOL = 0.0, VOH = 1.0) (typical)

 

<1.0 ns (VOL = -1.65, VOH = 3.7) (typical)

<95 ps (VOL = 0.0, VOH = 0.1) (typical)

<110 ps (VOL = 0.0, VOH = 1.0) (typical)

Transition Time Control

No

   Slew Rate Control Range

   Setting Resolution

Channel Output Levels

Amplitude/Resolution

0.25 to 5.35 Vp-p / 5 mV (from 23 Ω source impedance into 50 Ω)

0.25 to 3.9 Vp-p / 5 mV (from 50 Ω source impedance into 50 Ω)

0.50 to 7.8 Vp-p / 5 mV (from 50 Ω source impedance into 1 MΩ)

0.03 to 1.25 Vp-p / 5 mV (into 50 Ω)*3

0.06 to 2.5 Vp-p / 5 mV (into 1 MΩ)*3

Output Voltage Window

-1.65 V to 3.70 V (from 23 Ω source impedance into 50 Ω)

-1.2 V to 2.7 V (from 50 Ω source impedance into 50 Ω)

-2.4 V to 5.4 V (from 50 Ω source impedance into 1 MΩ)

-2.0 V to 2.47 V (into 50 Ω)

-2.0 V to 7.0 V (into 1 MΩ)

DC Accuracy

(±3% of the set value) ±50 mV into 50 Ω to GND

Limit setting

High- and low-level limits can be set

Maximum Output Current

±80 mA

Overshoot

<15% (typical) at High = 1.0 V, Low = 0 V

<10% (typical) at High = 1.0 V, Low = 0 V

Typical Support Native Logic

TTL, CMOS, (P)ECL, LVPECL

LVDS, CMOS, (P)ECL, LVPECL, CML

External Jitter Control

No

Yes

External Jitter control input channels and connectors

1 single-ended channel

1 SMA connector

2 single-ended channels

2 SMA connectors

Input range

-0.5 V to +0.5 V (typical)

Max input: -1.0 V to +1.0 V

-0.5 V to +0.5 V

Jitter Frequency

DC to 250 MHz *4

DC to 50 MHz

Jitter Amplitude

240 psp-p for 1 Vp-p input at Data rate ≤2.7 Gb/s*5

Range 1:

Up to 1 ns at 1 Vp-p

Range 2:

Up to 2 ns at 1 Vp-p

External Tri-state (Hi Z) Control

Yes (SMB input connector)

No

Tri-state Enable

Enable: Hi 3.3 V, Disable Lo: 0.0 V

Control Channels

By output module level

Delay Time from Inhibit In to Data Output

Active to Inhibit: 13 ns,

Inhibit to Active: 12 ns

*2 Minimum pulse width >2.86 ns.

*3 Maximum output amplitude is dependent on output voltage window (offset). (See Figure 1.)

*4 Up to 400 MHz by overdriving jitter input (max -1.0 V to +1.0 Vp-p). (See Figure 2.)

*5 Jitter amplitude at data rates >2.7 Gb/s calculated as {240 - 61.5 × (data rate - 2.7)} psp-p for 1 Vp-p input (see Figure 3).

Thumbnail

Figure 1. DTGM30, M31, M32 Output Amplitude vs. Offset

Thumbnail

Figure 2. DTGM31 Jitter Input Frequency Response

Thumbnail

Figure 3. DTGM31 Maximum Jitter Amplitude vs. Data Rate

 

 

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