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전화 문의

9:00am-6:00PM KST에 이용 가능

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매뉴얼, 데이터 시트, 소프트웨어 등을 다운로드할 수 있습니다.

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피드백

SDLA(시리얼 데이터 링크 분석)

신호 주파수 및 축소 진폭의 가속화로 인해 컴퓨터, 통신 및 메모리 버스를 테스트하는 데 있어 문제가 발생합니다. 텍트로닉스의 고급 시리얼 데이터 링크 분석 솔루션을 통해 제품을 출시하는 데 필요한 특성화, 컴플라이언스 및 디버깅 작업 사이를 원활하게 전환할 수 있습니다.

  • SDLA Visualizer for MSO/DPO70000 Series Real Time Oscilloscopes : SDLA Visualizer를 통해 전체 측정 회로 제외, 시뮬레이션 회로 포함 및 수신기 평준화 작업을 수행할 수 있습니다. DPOJET 지터 및 아이 분석과 함께 SDLA Visualizer를 사용하면 컴퓨터, 통신 및 메모리 버스에 대해 포괄적인 시뮬레이션 및 측정 환경을 제공할 수 있습니다.
Title
Correlation of Measurement and Simulation Results using IBIS-AMI Models on Measurement Instruments (DesignCon 2014)
Increasing serial bus data rates have resulted in requirements for de-embedding measurement circuits, embedding compliance channels, and applying reference equalizers to open closed data eyes for …
DesignCon 2015 Paper – Hybrid Modeled Measured Characterization of a 320 Gbit/s Backplane System
This paper explores a case study of a multilane Ethernet backplane 320 Gbit/s system that is difficult to fully measure and deembed, implements a hybrid method of modeling, deembedding, and …
Validation & Analysis of Complex Serial Bus Link Models (DesignCon 2013)
This paper highlights an application framework for performing serial data link modeling and analysis using live waveforms on a real-time oscilloscope. It then introduces a method for re-sampling S …
PCI Express Gen5 Automated Multi-Lane Testing
Comprehensive characterization of high-speed links such as PCI Express® require performing measurements of the Transmitter (Tx) and Receiver (Rx) across multiple differential lanes for the link under …
Serial Data Link Analysis
SDLA Visualizer software provides extensive capability for computing embed and de-embed filters for real-time measurement and simulation. This application note focuses on the embed and de-embed …
Equalization and Serial Data Link Analysis Methods (SDLA) with 80SJNB Advanced Application Note
This application note describes test and measurement methodology used by serial data standards running on lossy/dispersive channels which close the eye diagram at the receiver, and where equalization …
Title
PCI Express Gen 4 and Gen 5 Transmitter and Receiver Validation
PCI Express I/O bandwidth has doubled every 3 years on average thereby leading to an increased demand for this full duplex high speed bus architecture. As the industry begins deploying the 5.0 …
DDR5 Memory Characterization
While they promise to provide datacenters with large amounts of data at faster speeds and lower power consumption, DDR5 memory devices have unique test challenges.  Learn about characterization and …
Using SDLA Visualizer
Learn how to open closed eyes using equalization techniques and how to de-embed reflections and loss caused by the measurement setup using SDLA Visualizer for Tektronix Real-Time Oscilloscopes.
How to Address Your Toughest Serial Bus Design Challenges with EDA and Measurement Correlation
This Tektronix webinar will teach engineers how to use modeling tools to correlate simulations with high-speed physical layer measurements on Serial Bus Standards using the DPO/MSO70000 Series …
TDR Analysis for S Parameter Creation
This webinar reviews TDR basics and the ability to create S-parameters using TDR/TDT measurements to validate high speed channels for debug or de-embedding in a Serial Data Link Analysis application.
Advanced Jitter and Noise Analysis
 As serial data speeds increase, the need to perform accurate timing and jitter measurements is key to staying current in your design role. Check out this new webinar that covers advances in the …